View W562XXXDESIGNGUIDE_197091.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

W562XXX DESIGN GUIDE 2-tone Melody+ADPCM Voice Synthesizer (BandDirectorTM Family)
INTRODUCTION
The W562xxx is a family of multi-engine speech synthesizers. These synthesizers incorporate part of the following parts into a single chip: a simple 4-bit uC core (including RAM, register file, timer, interrupt control logic, ALU, and stack), speech synthesizers and Dual tone melody generator.
W529xx Cost W523x W583xx W581xx W528x Performance
Figure 0-1. Speech Synthesizer Spectrum
As shown in Figure 0-1, the W56xxx satisfies those applications of parallel processing requirements and especially of good quality melody effects. On the other hand, customers select PowerSpeech series (W528x, W523x, W581xx, W583xx, and W529xx) for the sake of cost issues. Also noted in Figure 0-1, the W56xxx family shows the same performance while spans into a wide range of cost structure. That's because the different components selected for a certain family member to fit specific applications. Typical applications for the W56xxx family are listed below: * Talking clocks * Toys * Direct-Mail Advertisements * Computer-aided instruction * Games * Edutainment toys * Gifts * Warning Systems
W56xxxx Family
-1-
Publication Release Date: Nov. 1999 Revision A3
W562XXX DESIGN GUIDE
Winbond supports the development for the W56xxx family as usual -- user friendly developing environment. Several development tools are provided in order to cut the time required to develop a code. They are ICE (In Circuit Emulator), Speech Coding System Version 7.53.2, and demo boards. The W56000 chip is used for the In Circuit Emulation for all of the family members. All of the derivatives of this family is a sub-set of the W56000 chip. GENERAL DESCRIPTION The W562xxx is a sub-set of the W56000. It consists of a 4-bit uC, two ADPCM synthesizer and one dual tone Melody generator. The internal 4-bit uC is composed of a 64-nibble RAM, and an 8-bit timer. The W562xxx is one of the derivatives of the W56000 family (the MIDI speech products with multi-engine capability). It is capable of processing C, speech synthesis, and dual tone Melody generation in parallel. The internal 4-bit C is a simple engine to execute instructions of up to 12 KIPS (Kilo-Instructions Per Second). Other engines are activated in parallel with the C to implement specific tasks, like speech syntheses and dual tone Melody generation. The dual channel operations (synth1 and synth2, or synth and dual tone Melody) is implemented by dedicated H/W only with the help of synth interrupts for concatenating voice segments and melody phrases automatically. The efforts in programming the speech equation is much like that of the PowerSpeech. User-friendly programming style is thus preserved under Winbond's speech coding system. The W562xxx is equipped with the W56000 ICE system, customers' programs can be debugged efficiently and effectively than ever.
PART NO. Sec. ROM (Kbit) PART NO. Sec. ROM (Kbit)
W562S08 8 256 W562S40 40 1216
W562S10 10 288 W562S50 50 1376
W562S12 12 320 W562S60 60 1536
W562S15 15 480 W562S80 80 2304
W562S20 20 576 W562S99 100 2688
W562S25 25 672 W562M02 120 3072
W562S30 30 768 -
There are 2 bodies in W562M-xx family for two chip solution, list as following.
Product # W562M-04 W562M-05 Duration 4 minutes 5 minutes ROM 6 Mbits 8 Mbits Chip Set Configuration W56000 + W55M06 W56000 + W55M08
Possible applications are: * Programmed voice synthesis with background music or speech. * I/O interactive voice synthesis to accompany with background music or speech. * Q&A games. * Edutainment toys. FEATURE
* Multi-engine processor parallel management with C, speech and Dual Tone Melody.
- C // (Synthesizer1 or Dual Tone Melody) // Synthesizer2 (//: in parallel )
-2-
W562XXX DESIGN GUIDE
- C, with basic ALU, 64-nibble RAM (including 8 working registers) and an 8-bit timer. - Synthesizer1 capable of voice syntheses with Sample rate @ 4.8/6/8/12 KHz - Synthesizer2, same as synthesizer1. - Dual-tone Melody D/A output with 3 level volume control
* Wide operating voltage range: 2.4 to 5.5 volts * Low power consumption (VDD = 5 Volt)
- Standby current < 1 A - Operating current < 1 mA
* Main oscillator: 3 MHz, Ring oscillation * Input/ Output port
- Port for input only: 1 port/ 4 pins - Input/ Output ports: 2 ports/ 8 pins - Port for output only: 1 port/ 4 pins - Can offer a direct row and column matrix of up to 72 (8 x 9) keys
* Interrupts
- Internal interrupts: Timer - External interrupts: TG (port 0, port1), POI (Power On Initialization) - Priority: POI > TG > Timer
* Melody + Voice outputs for DAC * TG interrupt provided
- Share TG interrupt for Port0/Port1 input - Global TG interrupt enable controlled (bit3 of the IER register) - Individual interrupt enable controlled (PER0 and PER1 registers)
* Built-in 8 bit programmable down count timer
- One of two internal clock frequencies can be selected - Desired Timer interval = (preset value+1) * 1/FT (FT: 32 Hz or 32 KHz dependent on the bit0 of the MODE register, at Fosc = 3 MHz)
* A total of around 64,000 instructions can be used in the program * Powerful instruction set:
- Arithmetic: ADD, ADDC, SUB, SUBC, INC, DEC, SETB, CLRB - Logic Operation: AND, OR, XOR, NOT - Shift & Rotate: RORC, ROLC, SHRC, SHLC - Date move: LD, LDR, MV - Branch: JP, JB0, JB1, JB2, JB3, JZ, JNZ, JC, JNC, JBZ1, JBZ2, CJNE, CJE, DJNZ, DJZ - Subroutine: CALL, RTN, RTI - Others: NOP, END, EN INT, DIS INT, PLAY CH1, PLAY CH2, STOP CH1, STOP CH2
* 8-level STACK shared by CALL, Timer, Synthesizer and TG * Multi-tasking operation via interrupt for automatic voice segment concatenation
-3-
W562XXX DESIGN GUIDE
- Melody or Speech voice can be easily concatenated with symbol "+" - Example: PLAY CH1, H4 + Melody1 + Speech1 + Speech2 + Melody2 + T4 The DAC of the W562xxx will play Melody1, Speech1, Speech2 and Melody2 sequentially
* The length of the voice segment is unlimited * Speech section control
- Sample rate control (4.8K/6K/8K/12K) - Example: PLAY CH2, H4 + speech1_S + T4; S: define the sample rate
* Melody section control
- Background music D/A output bits selectable for volume control (6/7/8) - Example: PLAY CH1, H4 + Melody_xxB + T4; B: define the melody output bits
* Dual tone melody with
- XM3: Triple harmonic effect - 3 kinds of percussion effects - 6 beats - 41 pitches from G3# to C7 - 16 kinds of tempo - The number of the score and note are unlimited
* Provide IR 38 KHz carrier
- TXF.0 = 0/1 disable/enable IR carrier - TXF.1 = 0/1 output carrier with P2.3 low/high active
* Provides ICE (In Circuit Emulation) system for easy debugging
- Free Run - Stop Run - Program Reset - Step Into - Step Over - Go To Cursor - Break point - Register read/ modify
-4-
W562XXX DESIGN GUIDE
W562xxx PAD DESCRIPTION Name P0.0 - P0.3 P1.0 - P1.3 P2.0 - P2.3 P3.0 - P3.3 DAC TEST OSC /RESET VSS VDD I/O I I/O I/O O O I I I Description TG pins, internally pulled high. I/O multiplexed port 0. Interruptable port if selected as input. I/O multiplexed port 1. status port only if selected as input. Output pins. Current output of mixing channel 1 and channel 2 for driving an external speaker. Test pin, internally pulled low. Connect ROSC to VDD to generate the 3 MHz master frequency Reset all, functions as POR, internally pulled high. Negative power supply. Positive power supply.
BLOCK DIAGRAM
P0 P1 P2 P3 OSC I/O Controller RAM Special Register Timing Generator
38KHz carrier
ALU
Timer
* ROM Synthesizer II Synthesizer I Dual Tone Melody Generator
Mixer
DAC
Figure 0-2. Block Diagram of W562xxx
-5-
W562XXX DESIGN GUIDE
FUNCTION DESCRIPTION The W562xxx is basically a subset of the W56000 ICE chip, which is a C-based speech processor with multi-tasking capability to implement the program control, voice synthesis, and dual tone Melody generation in parallel. There are maximum 8 external TG interrupts (P0 & P1) which are serviced upon the encountering of the falling-edge triggers. These TG input are different from Winbond's previous PowerSpeech owing to the interrupt essence, which means these TG inputs don't overwrite the current operation, but interrupt instead. After completion of the common ISR, the unfinished program that is interrupted by TG will be continued. The POI is another interrupt that executes automatically upon power up or depression of the RESET pin. A total of 8 x 9 keypad matrix can be formed by configuring 8 inputs (P0 & P1) , 8 outputs (P2 & P3) and ground without external components. The W562xxx can synthesize dual-channel voices with different sample rate or voice synthesis plus melody generation independently, meanwhile the control program proceeds to execute regardless of the dual-channel operation. For synchronization among the control program and voice syntheses, two busy flags (BZ1 & BZ2) concerning the status of the dual channels are available. Also, at the end of each voice segment synthesis or melody phrase generation, the H/W channel interrupt is generated to finish the playback of the channel list. After the completion of a channel list, each channel must be terminated by an identifier to mark "End Of List (EOL)." Should the EOL mark be encountered, the specific channel is said to enter the IDLE state, where the busy flag turns down at that moment. The sample rate used for each channel may be different to make efficient use of the memory space and to have an acceptable voice quality. For each channel list, there could be delays, which could be made by inserting silence of certain length, between successive voice segments or melody phrases to allow for better synchronization of the dual channel outputs. Because of the parallel processing capability of the W56000 family, customers now have the ability to change status of the output pins during the period of channel operation without sacrificing the continuation of voice combinations. The ALU together with the 64-nibble RAM of the W56XXX offers customers a great deal of flexibility to achieve various kind of program controls for different applications. The W562xxx program can be developed by customers themselves quite easily as PowerSpeechTM products. The developing environment is much the same with current Winbond's speech coding system. Besides, another powerful debugging tools, the W56000 ICE system, is provided to assist program development. Less effort, but high output is always the programming guideline for the W56000 family. P0.0 - P0.3 The P0 port is interruptable trigger inputs with separate internal pull-up devices. This port is usually regarded as TG1 - TG4 in previous PowerSpeech products. No internal debounce circuits is available with P0, since the bounce is to be eliminated by means of user's program. A common ISR, for P0 & P1 (provided that P1 is selected as input port), will be invoked once a low-going edge is sensed on the port, the program is then used to further differentiate which pin of the port is actually pressed down.
-6-
W562XXX DESIGN GUIDE
P1.0 - P1.3 These pins can be selected to be either inputs or outputs, depending on the status of IOR1 (I/O register 1). By setting the PCR1 (Pin Configuration Register 1), each selection can also be defined as passive pull-up or floating for input pins, or defined as inverter or open drain outputs. See Control Registers for further information. The P1 port is interruptable and invokes the same ISR as P0, if selected as input. P2.0 - P2.3 These pins can be selected to be either inputs or outputs, depending on the status of IOR2 (I/O register 2). By setting the PCR2 (Pin Configuration Register 2), each selection can also be defined as passive pull-up or floating for input pins, or defined as inverter or open drain outputs. See Control Registers for further information. The P2 port is a status port (not interruptable, users have to move it to internal RAM for further processing), if selected as input. P3.0 - P3.3 The P3 is an inverter type output port. VDD & VSS VDD is the positive power supply, while VSS is the negative power supply. In order to prevent possible power noises generated during motor driving from interfering the proper operations of the internal POR circuit, which is essential to the POI(Power On Initialization) process of the PowerSpeech synthesizers, two approaches are being adopted in the W562xxx one is to use the /RESET pin, which is described in detail elsewhere, to fully reset the internal circuit for a brand new start; the other is to place VDD and POR circuit apart as far as possible to reduce the possibility of noise induction. In order for the W562xxx to process the POI correctly, the VDD has to drop low enough and rise quite quickly to initiate the internal POR circuit for generating the required pulse. Special care goes to the discharge of VDD to nearly ground level to ensure proper operations. TEST The TEST pin is used solely for test purposes. It is internally pulled low by an NMOS device with a 200K resistance to prevent floating-gate conditions. /RESET Active low reset input with an internal pull-high resistance of 500 K. The falling edge of the /RESET pin will reset the W56XXX totally, just like the POR condition. Right at the rising edge of the /RESET input, the W56XXX starts to awake and proceeds to undergo the POI process. Originally, the /RESET pin is used to function as a last resort to rescue the POR failure issue, which is encountered in some occasions where the internal POR circuit of the W56XXX can't operate properly. If customers failed to discharge the VDD to ground level and re-power up the W56XXX, it may function abnormally, causing unpredictable operations. Users may then reset the W56XXX by sending a pulse through the /RESET pin to re-start the operation from
-7-
W562XXX DESIGN GUIDE
the very beginning: POI. Maybe, this is the safest way to get around all the annoying POR issues.
DAC The DAC pin is a current-type voice output, which is connected to the output of the internal D/A converter. The full scale output of the 8-bit D/A converter is 5 mA, which is able to drive the external 8-W speaker through the amplification of a low-power NPN transistor with a of around 120 - 160. ( Usually, the selection of an 8050D transistor is appropriate. )
DAC C
8050D NPN transistor
R
Figure 0-3. DAC Current-type Voice Output
The shunt resistor R in Figure 0-3 is used to reduce the current that enters into the base of the NPN transistor for driving the external speaker without distortions, which may occur in the above simple scheme. Distortions result from two facts: one is the saturation phenomenon of the transistor due to large IB, the other is the introduction of R that cuts small signals too much out of the original waveform. A typical value of the shunt resistor is around 470Ohm - 1KOhm . The smaller the resistance, the smaller the current enters the transistor and vice versa. Users have to trade off what value of R could be added without causing these two kind of distortions. The capacitor C is used for low-pass filtering the unwanted high-frequency noises that are generated from D/A converters during sample transitions. Users may adjust the capacitance to reach a better perceptual hearing. It could be simply omitted without affecting the voice quality too much. OSC The master frequency (3 Mhz) of the W562xxx can be generated by ring oscillator. Connect OSC to VDD via ROSC.
ABSOLUTE MAXIMUM RATINGS ITEM SYMBOL CONDITIONS RATED VALUE Power Supply VDD - VSS -0.3 - +7.0 Input Voltage VIN All Inputs VSS-0.3 - VDD+0.3 Storage Temp. TSTG -55 - +150 Operating Temp. TOPR 0 - +70 NOTE: Operating the device under conditions beyond those indicated above may cause permanent damage or affect device reliability. UNIT V V C C
-8-
W562XXX DESIGN GUIDE
ELECTRICAL CHARACTERISTICS
DC PARAMETERS
(VDD-VSS = 3.0V, Fm = 3 MHz, TA = 25 C; unless otherwise specified)
PARAMETER Operating Voltage Standby Current Operating Current ( Crystal Type ) Operating Current ( Ring Type ) Input Low Voltage Input High Voltage Input Current for P0, P1,P2 Input Current for /RESET Output Current of P1, P2, P3 DAC (D/A full Scale) Pull-low Resistor
SYM. VDD IDD1 IOP1 IOP2 VIL VIH IIN IIN1 IOL IOH IDAC RPL
CONDITIONS No load, No Playing @5V No load
MIN. 2.4 -
TYP. -5.0 -
MAX. 5.5 2 1 1 0.3VDD VDD -6 -6 -6.0 -
UNIT V A
mA
No load All Input Pins All Input Pins VDD = 3V, VIN = 0V VDD = 3V, VIN = 0V VDD = 3V, VOUT = 0.4V VDD = 3V, VOUT = 2.7V VDD = 4.5V, RL = 100 TEST, OSCSEL Pins VSS 0.7VDD 5 -3 -4.0 100 mA V V A A mA mA mA K
-9-
W562XXX DESIGN GUIDE
AC PARAMETERS
PARAMETER Main-clock Frequency
SYM. FM f f TINS TPOR
CONDITIONS Ring type, ROSC = 1.2M @3V,1.1M@4.5V f(3V) - f(2.4V) f(3V) One machine cycle -
MIN. 2.7
TYP. 3
MAX. 3.3
UNIT MHz
Frequency Deviation by Voltage Drop for Ring Type Oscillator Instruction Cycle Time POR Pulse Width
-
-
10
%
1/12K 1
-
1/3K -
S mS
TYPICAL APPLICATION ( for your reference only)
Vcc
P0.0 P0.1 P0.2 P0.3 P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2
W562xx
DAC
Rs Cs 8050
Vcc
R2
IR LED P2.3 Vcc R1 P3.1 OSCI
R OSC
8550
RESET
Figure 0-4. Application Circuit of W562xxx
- 10 -
W562XXX DESIGN GUIDE
ARCHITECTURE
This section discusses the internal architecture of W562xxx. Following chart shows the major components of the W562xxx devices' internal architecture.
RAM and Registers
0x00 - 0x07 0x08 - 0x3F 0x40 - 0x5F 0x60 - 0xFF Working RAM General-purpose RAM Control Register ICE Register
The built-in RAM and registers map to the same address lines, which is called memory (RAM) mapped registers. The registers comprise three major parts: 1) control registers, like ACC & IOR; 2) internal registers, like SAR, CLP, STACK, and OPTION registers. They are used for ICE debugging purposes The first 128 RAM-mapped locations are 4-bit wide and are suitable for data exchanges. The last 128 addresses are used for those registers that got more than 4 bits. RAM 64 x 4 bits RAM, R0..R63, can be used to store data. They can only be addressed directly. The first eight locations, R0..R7, are used as Working Register (WR), denote as WR0 to WR7. They are useful in data moves from other RAM-mapped locations. For convenience, users can denote WR0 ~ WR7 as R0 ~ R7 to load data directly, and then rename to WR0 ~ WR7 for moving the data. The other data memories are used as general memory and can't operate directly with another RAM. Example : (1) Load data LD R10, 1001b (2) Load & Move data LD R2, 1001b MV R63, WR2 Control Registers ACC The ACC (Accumulator) is generally modified during MOVE and ALU operations to reflect the operation result. Branch instructions can be decided to be executed or not depending on the ACC content. ; Working Register location 2 (WR2) is named as R2 for loading ; data into it , and then renamed to WR2 to move data to R63. ; the 4 bit value is loaded into the addressed location 10.
- 11 -
W562XXX DESIGN GUIDE
MODE 3 x 2 x 1 x 0 Timer clock
Default vaules upon power up are "0000", indicating clock source of timer is 32 Hz. MODE.0 0 1 Example : LD MODE, 1101b ; bit1, 2, and 3 are don't care ; clock source of Timer is 32 Khz Clock Source 32 Hz 32 KHz Overflow Period 30 mS - 8 S 30 uS - 8 mS
IER 3 Timer 0: Disable (Default) 1: Enable If an interrupt source is disabled, the corresponding ISR (Interrupt Service Routine) won't be invoked upon the occurrence. Example : LD IER, 1100b 2 TG 1 Reserved 0 Reserved
; Timer & Trigger interrupt are enable,
PER0 (Port Enable Register 0) 3 P0.3 0: Disable (default) 1: Enable The PER0 (Port Enable Register 0) defines the enable/disable condition for the falling-edge trigger of each P0 pin. Example : LD PER0, 0011b PER1 ( Port Enable Register 1 ) 3 P1.3 0: Disable (default) 1: Enable The PER1 (Port Enable Register 1) defines the enable/disable condition for the falling-edge trigger of each P1 pin when P1 is configured as input port. Example : LD PER1, 1100b ; Pins P1.0 and P1.1 are disable 2 P1.2 1 P1.1 0 P1.0 ; The pins P0.2 and P0.3 are disable. 2 P0.2 1 P0.1 0 P0.0
- 12 -
W562XXX DESIGN GUIDE
P1 ( Port 1 Register ) 3 P1.3 2 P1.2 1 P1.1 0 P1.0
P1 is used for storing output values, provided that some pins of the port 1 is selected as outputs. P2 ( Port 2 Register ) 3 P2.3 2 P2.2 1 P2.1 0 P2.0
P2 is used for storing output values, provided that some pins of the port 2 is selected as outputs. P3 ( Port 3 Register ) 3 P3.3 2 P3.2 1 P3.1 0 P3.0
P3 is used for storing output values of the port 3. IOR1 ( I/O Register 1 ) 3 P1.3 2 P1.2 1 P1.1 0 P1.0
0: Input (Default) 1: Output This register is used to specify the selection of input or output of P1.0 - P1.3 pins of port P1. A "0" selects input, while a "1" gives the output selection. Default value of IOR1 is 00h(after power on, or reset), which indicates the selection of all inputs, to avoid possible I/O conflicts with external circuits that may cause large current consumption. Example : LD IOR1, 1100b ; input pins : P1.0, P1.1 ; output pins : P1.2, P1.3 Once a pin was configured as input pin and Hi impedance (by set 0 in related bit of PCR1 or PCR2 register), this pin must not leave as floating to avoid large standby current. IOR2 ( I/O Register 2 ) 3 P2.3 2 P2.2 1 P2.1 0 P2.0
Same as IOR1 except for the selection of port P2, rather than port P1. Example : LD IOR2, 1111b ; port 2 is configured as output port PCR1 ( Port Configuration Register 1 ) 3 P1.3 2 P1.2 1 P1.1 0 P1.0
- 13 -
W562XXX DESIGN GUIDE
Defaults are "0" upon power up. Together with IOR1, the state of port P1 can be configured as follows: Pin Function Input, High Z Input, Internal Pullup Output, Inverter Output, Inverter Output, Open Drain Output, Open Drain Example : LD IOR1, 1111b LD PCR1, 0000b LD P1, 1111b ; P1 is configured as an open-drain output port with ; high Z state P1 x x 0 1 0 1 PCR1 0 1 1 1 0 0 IOR1 0 0 1 1 1 1 Pin State High Z Passive Pull-up 0 1 0 High Z
PCR2 ( Port Configuration Register 2 ) 3 P2.3 2 P2.2 1 P2.1 0 P2.0
This register is used to configure the I/O type of port P2. PSR ( Processor Status Register ) PSR.3 BZ2 Read only PSR.2 BZ1 PSR.1 Carry Read / Write PSR.0 Zero Read only
0: False (Default upon power up) 1: True BZ2 : busy or not of channel 2. BZ1 : busy or not of channel 1. Carry : carry flag is set or not. Zero : zero flag is set or not ( default is 1 ). The PSR register needs to be stored first after an interrupt happens along with general-purpose ACC in order to prevent from possible changes made during ISR. They must be moved from temporarily stored RAM locations to PSR and ACC for restoring initial values correctly. Example : SETB PSR.1 ; set the carry flag (CF) to 1
- 14 -
W562XXX DESIGN GUIDE
TF0 ( Trigger Flag of Port 0 ) TF0 is used to latch the individual trigger event of port 0 (pins P0.0 - P0.3). TF0 register is organized as 4-bit binary register (TF0.0 to TF0.3). It can be read or cleared by "MV WRn , TF0", and "CLR TF0" instructions. The bit descriptions are as follows: 3 P0.3 Bit 0 = 1 Bit 1 = 1 Bit 2 = 1 Bit 3 = 1 Falling-edge detected on P0.0 Falling-edge detected on P0.1 Falling-edge detected on P0.2 Falling-edge detected on P0.3 2 P0.2 1 P0.1 0 P0.0
Default value is 0000B upon power up. Since each bit of TF0 will be set up to 1 whenever a falling-edge is detected on the corresponding pin ( no debounce time). The TF0 must be cleared immediately after the ISR of dedicated TG interrupt is successfully invoked to prevent the undesired disturbance which may be caused by glitch on port 0 ( see more detail in Program Example section). Example : CLR TF0 CLRB TF0.1 TF1 ( Trigger Flag of Port 1 ) 3 P1.3 2 P1.2 1 P1.1 0 P1.0 ; clear the TF0 register ; clear TF0 bit1
Same as TF0 except for port P1, rather than port P0, when P1 is configured as trigger interrupt input.
TXF ( Transmit enable flag ) 3 reserved 2 reserved 1 with low/high active 0 disable/enable 38KHz carrier
TXF.0 define IR carrier enable or not = 0 disable IR 38KHz carrier = 1 enable IR 38KHz carrier TXF.1 define IR carrier with low or high active = 0 P2.3 low active with 38KHz carrier = 1 P2.3 high active with 38KHz carrier default value (TXF.0, TXF.1) = ( 0, 0 ) Control register v.s. P2.3 output waveform
- 15 -
W562XXX DESIGN GUIDE
program
P2.3 output waveform
SETB TXF.0 ; enable IR carry CLRB TXF.1 ; with low carrier CALL PATTERN 38KHz
SETB TXF.0 ; enable IR carry SETB TXF.1 ; with high carrier CALL PATTERN 38KHz
CLRB TXF.0 ; disable IR carry ;SETB TXF.1 ; don't care TXF.1 ; state, as the normal output pin CALL PATTERN
PATTERN: SETB P2.3 CALL DELY5MS CLRB P2.3 CALL DELY2MS SETB P2.3 CALL DELY2MS CLRB P2.3 CALL DELY2MS SETB P2.3
CALL DELY2MS CLRB P2.3 CALL DELY2MS SETB P2.3 CALL DELY2MS CLRB P2.3 CALL DELY2MS RTN
TIMER 7 6 5 4 3 2 1 0
This 8-bit timer downcounts every clock cycle, which is determined by the timer clock source. Upon overflow conditions that occur when the timer changes from 00h to FFh, the W56000 generates the timer INT to allow manipulation of timed events. It starts to downcount after the execution of "LD timer, operand". After the timer INT occurs under overflow conditions, the timer
- 16 -
W562XXX DESIGN GUIDE
stops downcounting. Users have to re-start the timer operation by loading the timer with an appropriate value. The timer interrupt happens every 30 uS - 8 second, depending on the selection of different clock sources, and can be disabled by IER. Example : LD TIMER, 080h ............... ............... TIMER_INTERRUPT : ........ LD TIMER, 080h ......... RTI ; load the period of timer into TIMER register ; and the timer starts downcounting ; timer interrupt entry ; re-start the counting ; return from interrupt
TEMPO
The tempo of W562xxx can not be dynamically controlled by register as well as if the Fix Beat Length of the Melody Converter was set then the tempo will be changed automatically. The tempo of W562xxx as listing below: bpm (beat per minute) 1091 546 121 109
364 99
273 91
218 84
182 78
156 73
136 68
Memory Partition
The W56000 divides the external memory space into several different partitions for the purpose of dual-channel operation along with the program execution, they are: Option, IV (Interrupt Vector), COLA (Channel Operation List Area), Control Program, and ADPCM/note. 0x0000 0x0002 Option Interrupt Vector Reserved Area 0x0020 Channel Operation List Area 0x0100 Control Program Flexible size Fixed size
ADPCM/PCM/Note
- 17 -
W562XXX DESIGN GUIDE
Figure 0-5. Memory Partition
Operation Flow
Power On Booting Operation
POI
Yes
Reset ?
Power Down No No Interrupt ? Yes
Figure 0-6. Operation Flow Chat
The Figure 0-6. shows the operation flow chart of W56xxx device. The W562xxx enters power down (or called standby) mode if and only if the following conditions are met: 1) END instruction executed; 2) Dual-channel operations cease; 3) Timer disabled or not activated since last overflow. After entering the power down mode, only /RESET and TG interrupts can wake up the W56xxx. Followings are two typical procedures to get in/out of the power down mode. 1) Power on => Boot (Option < 200 mS) => POI => Operation => Power down. 2) Power down mode => Wake up (RESET, TG interrupt) => Operation => Power down.
Interrupt
Keyword POI: Reserved TG: Timer_interrupt: Name POR/Reset Reserved TG Timer Address 002H 008H 00AH 00CH Instruction JP POI Reserved JP TG JP Timer_interrupt
Table 0-1. Interrupt vector
When an ISR (Interrupt Service Routine) is in service, others (TG, Timer) are disabled by H/W automatically. Only if otherwise enabled by S/W program through instructions that modify content of IER, like "LD IER, operand", (the disable condition be released by this instruction upon the updating of IER), or enable interrupt EN INT , other interrupts (except for POR) are disabled until the reaching of RTI (interrupt enabled again by H/W automatically), which indicates the finish of an ISR. Special care goes to the prevention of STACK overflow, since only maximum 8-level stack register is shared among all interrupt sources, and CALL instruction. The POR/Reset is Non-Maskable Interrupt (NMI). The program execution and channel operations all return to initial states as in power up conditions.
- 18 -
W562XXX DESIGN GUIDE
Other interrupt sources are processed in a polling sequence of the priority: TG => Timer, if occur simultaneously. If an interrupt is disabled during ISR of other interrupts, it is latched and shall be serviced right after the release of the disable condition. Trigger Since all P0 & P1 triggers share the same TG interrupt vector, users have to further differentiate the real one from others by programming. Also, trigger debounce should be considered in the TG section. Though a little bit complex than PowerSpeech, which is done by H/W debounce circuit, but on the other hand, it do mean more flexibility.
TG
IR PER0.0 TF0.0 P0.0 PER0.1 DQ ck R PER0.2 DQ ck R PER0.3 DQ ck R PER1.0 DQ ck R PER1.1 DQ ck R PER1.2 DQ ck R PER1.3 DQ ck R TF1.3 TF1.2 TF1.1 TF1.0 TF0.3 TF0.2 TF0.1 DQ ck R IR
Data Bus
P0.1
IR
P0.2
IR
P0.3
IR
P1.0
IR
P1.1
IR
P1.2
IR
P1.3
Reset CLR TF0 Reset CLR TF1
Figure 0-7. Trigger Scheme
Figure 0-7 shows the structure of trigger scheme. Two program examples based on this structure is listed below to show how to configure the ISR for trigger interrupt. Example (1) : Use port 0 as interrupt source TG: MV WR0, P0 CJE R0, 1111B, BACK MV WR1, TF0 CJE R1, 0000B, BACK call debounce XOR P0, WR0 JZ SCAN0 ; TG is keyword.
; Software debounce used to prevent the glitch on port 0
- 19 -
W562XXX DESIGN GUIDE
BACK: CLR TF0 RTI SCAN0: MV WR0, TF0 MV ACC, WR0 CLR TF0 JB0 P00 JB1 P01 JB2 P02 JB3 P03 RTI P00: PLAY CH1, H4+some_2+T4 RTI P01: PLAY CH1, H4+arround_2+T4 RTI P02: PLAY CH1, H4+feel_2+T4 RTI P03: PLAY CH1, H4+dance_2+T4 RTI debounce: LD R11, 0111b a: LD R12, 1111b b: DJNZ R12, b DJNZ R11, a RTN ; differentiate which pin of port 0 is the real one trigger source.
; ISR for trigger source P0.0
; ISR for trigger source P0.1
; ISR for trigger source P0.2
; ISR for trigger source P0.3
; soft ware debounce, a delay time of about ; 512 instructions cycle time = 40 mS
Example (2) : Use both port 0 and port 1 as trigger source TG: MV WR0, P0 CJE R0, 1111B, TRIG1 MV WR1, TF0 CJE R1, 0000B, TRIG1 call debounce XOR P0, WR0 JZ SCAN0 TRIG1: CLR TF0 MV WR0, P1 CJE R0, 1111B, BACK MV WR1, TF1 CJE R1, 0000B, BACK ; TG is keyword.
; software debounce for port 1
- 20 -
W562XXX DESIGN GUIDE
call debounce XOR P1, WR0 JZ SCAN1 BACK: CLR TF1 RTI SCAN0: MV WR0, TF0 MV ACC, WR0 CLR TF0 JB0 P00 JB1 P01 JB2 P02 JB3 P03 RTI SCAN1: MV WR0, TF1 MV ACC, WR0 CLR TF1 JB0 P10 JB1 P11 JB2 P12 JB3 P13 RTI ; differentiate which pin of port 1 is the real one trigger source
Timer The timer of the W56xxx is a quite simple mechanism to facilitate applications with timed events. Once the timer interrupt is enabled, the timer starts to down-count as long as the "LD timer, operand" is executed. Upon reaching the overflow condition, the timer interrupt occurs and the timer_interrupt subroutine is serviced. Users have to re-load the timer with a new value in order to start the timer again, since there's no auto-reload function in it. Interrupt Control During the period of a specific ISR, other interrupts except for POR & synth are disabled by H/W automatically. Users may enable certain interrupts under S/W control: "LD IER, operand", or "EN INT". Under normal conditions, the disabled interrupt situation disappears automatically when RTI of that specific ISR is encountered. Figure 0-8 shows the arbitrator of all the interrupt sources.
- 21 -
W562XXX DESIGN GUIDE
Reset EN INT LD IER, i RTI
Enable
TG IER.2
S
Q
R
Reset
Interrupt Controller
IV
Time r
S
Q
IER.3
R
Reset
Disable DIS INT
Figure 0-8. Interrupt Arbitrator
Speech Synthesis
The W562xxx offers two ADPCM synthesizers, synth1 and synth2, for voice reproduction. The operation of the synthesizers are the same as Winbond's PowerSpeech devices, and are description as below. Channel Operation List (COL) A Channel Operation (CO), which could be a voice segment, certain period of silence, or a melody phrase, is used to indicate what a channel is to playback with. A COL (Channel Operation List) contains a list of as many CO's as customers' needs for a certain channel, channel 1 or channel 2. The following example shows two COLs for channel 1 and channel 2, respectively. Ch1: H4 + V1 + Song1 + Song2 + V2 + T4 Ch2: H4 + V1 + V2 + [silence] + V3 + T4 Where H4, T4 are the head file and tail file of ADPCM/melody voice data. And V1, V2, V3 are voice segments (*.wam or *.src); [silence] is certain period of silence; Song1 and Song2 are melody phases (*.dm). There are many head and tail files for your option: H4/T4, H41/T41, H42/T42, and H43/T43 which can make sound smoothly in order to prevent the "pop" sound. The silence length is represented by 2's complement of the actual length in unit of (3khz)-1 due to the essence of up counting, instead of down counting. The W562xxx is said to finish the counting of the silence length, if overflow condition occurs. Since the width of the register that holds the silence length is 16 bit, the maximum silence length that can be implemented with each CO is 64
- 22 -
W562XXX DESIGN GUIDE
* 1024 * (3khz)-1 = 21.8 second. Of course, if customer really wants longer silence length, just add more CO's. For example : PLAY CH1, h4+[ 0BB8]+t4 ;denote the channel is playing a silence with a period of 1 second. Section Control The W562xxx provides various sampling frequencies for ADPCM speech synthesis which can be set by the section control function in the channel operation. The variable frequency which is provided for ADPCM synthesis are listed below: Option 0 1 2 3 SR ADPCM 4.8 KHz 6 KHz 8 KHz 12 KHz
Table 0-2. Sampling frequency
The syntax of section control is listed below :
PLAY CH1/ CH2, h4 + voice_s + t4
section control sampling rate
Three examples are given to show how the section control works. Example (1) : PLAY CH1, h4 + V1_ 3+t4 Example (2) : PLAY CH1, h4 + V1_ 2+t4
; the voice V1 is played back with a sampling rate of ; 12 KHz ; the voice V1 is played back with the sampling rate ; of 8 KHz
Dual Tone Melody Generation
W562xxx provides the D/A output bit selection: 6/ 7/ 8 bits option. The max. volume is 8 and 6 is the min. volume. While W562xxx is only playing the melody the 8 bits will make the volume loud. If melody just as the background music, the 6 bits will make the music more tender. It is controlled like following example: play ch1,h4+melody_xx6+t4 play ch1,h4+melody_xx7+t4 play ch1,h4+melody_xx8+t4 xx: means don't care. There are some concerned points when we are handling W562xxx dual tone melody: 1) Pitch window: from G3# to C7 2) Every note's beat length must be more than 1/4 beat.
- 23 -
W562XXX DESIGN GUIDE
3) If you selected the "fix beat length" all the notes will be reserved, even less than 1/4 beat, but it will occupy more ROM size. 4) If you heared a "pop" sound at the end of the melody. The last note of the melody must take longer duration to prevent the "pop" sound. W562xxx need 2.5 sec to decay the notes volume to DC level. 5) track1 and track2 can't used the same pitch at the same time. The notes will disappear or have the smaller volume. 6) NH4/NT4 will make W562xxx error, please used H4/T4, H41/T41, H42/T42, or H43/T43. 7) Anytime of track1 and track2 only have one note. Else, converter will select one of notes from track1/track2 automatically to make *.dm file. 8)
? 4
? 8
? 2
Following above rules, W562xxx will play the complete and perfect dual tone melody.
Basic Structure of the W56xxx Program
A program is usually divided into 4 areas: Body Declaration, Constant Area, Macro Area, and Command Area. It may contain a structure as below: Body Body declares here Body Declaration
CONSTANT Constant area starts here Constant Area
MACRO Macro Macro Area area starts here
CODE Command area starts here Command Area
- 24 -
W562XXX DESIGN GUIDE
Body Declaration Body has to declare first in the program to acknowledge the IC body type and ROM size used. Missing body declaration will cause a compilation error. The body type supported now are listed below. BODY W562S08 W562S10 W562S12 W562S15 W562S20 W562S25 W562S30 W562S40 W562S50 W562S60 W562S80 W562S99 W562M02 Note: Body release is subject to change without prior notice. For exact information, please check with Winbond's sales representatives. Constant Area SYNTAX DEFINE A constant name is a user-defined symbol. Refer to 0 for syntax of symbol. Value can be of different types, register, number, channel, clp, ram or wr. Please refer to section 0 for type information. The Assembler, basically, substitutes the with the while it parses through Command Area. NOTE: The assembler is not case-sensitive. For example: Define Define Define Define BUFFER1 BUFFER2 BUFFER3 FLAG1 32H R13 WR3 1011B ;/ Define value of Buffer 1 as immediate value 32H. ;/ Define value of Buffer 2 as the 13th RAM. ;/ Define value of Buffer 3 as the 3rd WR. ;/ Define value of FLAG 2 as immediate value 1011B.
Macro Area The Macro Area may consist of several macro declarations or none. After the macro has been defined, the macro name can be called in the program. While compiling, the assembler will look for the macro name, and expand it to the commands it defines. The syntax of macro declaration is described.
SYNTAX MACRO ENDM
- 25 -
W562XXX DESIGN GUIDE
A macro name is a user-defined symbol. Refer to section 0 for the syntax of symbol. Macro may have no arguments, or several arguments. Commands are used to separate between arguments. An argument is a user-defined symbol. The maximum number of arguments are 20. Macro should contain at least one command. Labels and directives are not allowed in macro, and macro can not be nested. In short, a macro command can not be a macro declaration. However, a macro command can use arguments, which will then be substituted by the parameters of a macro call, for operands. For example: MACRO ADD2 arg1, arg2 ADD arg1, arg2 ENDM ;/ Define the macro name as ADD2. ;/ Define 2 arguments, arg1 and arg2. ;/ Define macro command ADD.
Command Area The Command Area may consist of several commands and/or directives. The syntax of a command is described as follows SYNTAX A label is a user-defined symbol that is followed by a colon. It is not a mandatory part of the program. The label is used to name a program location, and to label entry, skipping and branching of the program. It can be used to change the order of program execution by using commands, such as JP and CALL, to jump to locations or call routines. After the program is compiled, all labels are converted into absolute address values. Program labels make it easy to find and remember program locations without having to compute the memory address. It is convenient for modifying a program. Mnemonics are reserved names for instruction op codes. is optional. Operands provide the data for mnemonics to act on. There may be from zero to three operands, depending on the op code, and they are separated by commas. Operands take the form of either literals or symbols for data items. Symbols are assumed to be assigned to data items declared in the Constant Area. Operands can be of the following types: 1. Symbol
- 26 -
W562XXX DESIGN GUIDE
An symbol is an alpha-numeric string (0~9, a z, A Z, and _ ) that starts with an alphabetic character and is allowed a maximum length of 40 characters. It must not be a keyword, or a predefined symbol name. 2. Number Numbers, or immediate values, accept four forms: Binary: Binary numbers are base 2 numbers, and are represented by a string of binary digits followed by the character B. A binary digit is a character from {0, 1}. For example, 0101B is equivalent to the decimal number 9. Octal: Octal numbers are base 8 numbers, and are represented by a string of octal digits followed by the character O. An octal digit is a character from {0-7}. For example, 11O is equivalent to the decimal number 8. Decimal: Decimal numbers are base 10 numbers, and are represented by a string of decimal digits. A decimal digit is a character from {0-9}. Hexadecimal: Hexadecimal numbers are base 16 numbers, and are represented by a string of hexadecimal digits followed by the character H. A hexadecimal digit is a character from {0-9, a-f, A-F}. A leading zero should be added if the hexadecimal number begins with one of digits {a-f, A-F}. For example, 0AH is equivalent to the decimal number 15. 3. RAM RAMs begin with a character R, and followed by a decimal number from 0 to 63. It is used to store data, and move data from/to any other RAM-mapped locations. The first eight locations of RAM, also called Working Registers (WR). RAMs can only be addressed directly. For example, R10 is the location 10 in RAM. 4. Working Register Working Registers begin with characters WR, and followed by a decimal number from 0 to 7. It is actually RAM mapped locations from 0 to 7. Working Registers can only be addressed directly. For example, WR0 is the location 0 in RAM.
- 27 -
W562XXX DESIGN GUIDE
5. Register Register names are reserved names. Refer to for more details. A list of registers is provided. REGISTER ACC MODE IER PER0 PER1 P0 P1 P2 P3 IOR1 IOR2 PCR1 PCR2 VOL1 VOL2 PSR TIMER TXF DESCRIPTION Accumulator Mode Register Interrupt Enable Register Port Enable Register 0 Port Enable Register 1 Port 0 Register Port 1 Register Port 2 Register Port 3 Register I/O Register 1 I/O Register 2 Pin Configuration Register 1 Pin Configuration Register 2 Volume 1 Register Volume 2 Register Processor Status Register Timer Register Transmit enable flag
6. Channel Channels are used to identify which channel is used for voice output. Channels start with characters CH, and followed by number 1 or 2. For example: PLAY CH1, RING is to output a voice RING to channel 1. 7. Channel List Pointer Channel List pointers are used to identify which channel list pointer is used. Channel List pointers start with characters CLP, and followed by number 1 or 2.
A good comment is a basic part in writing a program. The comments allow users to give the necessary explanations of commands. A comment starts with a semi-colon, and followed by any characters. The assembler will ignore a comment till end of the line. Directives are also called pseudo instructions. The W56xxx Assembler provides several directives:
- 28 -
W562XXX DESIGN GUIDE
1. Define frequency This directive is used to define the sample frequency. SYNTAX FREQ n It is the sample frequency of voice output, n= 0 to 3. For example: FREQ 3
; Define the sample frequency of voice output as 3.
2. Play voices This directive is used to play voices. It actually will expand into 4 commands: STOP LD , RD PLAY SYNTAX PLAY , Specify which channel to be output to. Only Ch1 and Ch2 are valid. Voice list may contain voice files, and/or length of silence for channel output. A voice file can be of two types: ADPCM (*.wam), or dual tone Melody(*.dm). The extension of voice file is not needed, the Assembler will automatically look for the voice files available in the local directory. A list of voices are separated by a +. For example: PLAY ch1, H4+Happy+[15]+Birthday+T4 ; Output 4 voice files, H4, Happy, Birthday, and T4, ; and a silence length 15h. Furthermore, when the voice list contains a large number of voice files , 50 files or more, and can't be placed in one line in text editor, the voice list can be separated into several lines and connected by the notation "\". The assembler will look it as a single list. For example: PLAY ch1, H4+Happy+[15]+Birthday+bird \ +cat+dog+A+B+ \ C+T4
- 29 -
W562XXX DESIGN GUIDE
are the same as PLAY ch1, H4+Happy+[15]+Birthday+bird+cat+dog+A+B+C+T4
3. Declare speech This directive is used to declare the type of speech files. From Speech Coding System Ver 7.54, ADPCM speech is the default speech file. All legal file type, for example, PCM files and WAV files, will be automatically converted to ADPCM files before compiling into .OBJ file. However, explicitly declaring speech file type, will retain the file type. Explicitly declaration will ensure the correct speech files will be used. SYNTAX SRC/WAM/DM/TM { , } It is the speech filename without extention name. For example: WAM dog DM singing
; define the ADPCM speech file. (default) ; define the dual Tone melody file.
- 30 -
W562XXX DESIGN GUIDE
INSTRUCTION SET
Instruction Set List
Mnemonics Arithmetic ADD Rn, i ADDC Rn, i ADD Rn, WR ADDC Rn, WR SUB Rn, i SUBC Rn, i SUB Rn, WR SUBC Rn, WR INC Rn DEC Rn SETB Rn.b CLRB Rn.b Logic Operations AND Rn, i AND Rn, WR OR Rn, i OR Rn, WR XOR Rn, i XOR Rn, WR NOT Rn Shift & Rotate RORC Rn ACC.b, Rn.b <-- Rn.(b+1); ACC.3, Rn. 3 <-- carry, carry <-- Rn.0 ROLC Rn ACC.b, Rn.b <-- Rn.(b-1),; ACC.0, Rn. 0 <-- carry, carry <-- Rn.3 SHRC Rn ACC.b, Rn.b <-- Rn.(b+1), ACC.3, Rn. 3 <-- 0, carry <-- Rn.0 SHLC Rn ACC.b, Rn.b <-- Rn.(b-1), ACC.0, Rn. Carry 1 Carry 1 Carry 1 Carry 1 ACC, Rn <-- Rn & i ACC, Rn <-- Rn & WR ACC, Rn <-- Rn | i ACC, Rn <-- Rn | WR ACC, Rn <-- Rn ^ i ACC, Rn <-- Rn ^ WR ACC,Rn <-- 1's complement of Rn Zero Zero Zero Zero Zero Zero Zero 1 1 1 1 1 1 1 ACC, Rn <-- Rn + i ACC, Rn <-- Rn + i + carry ACC, Rn <-- Rn + WR ACC, Rn <-- Rn + WR + carry ACC, Rn <-- Rn - i ACC, Rn <-- Rn - i - carry ACC, Rn <-- Rn - WR ACC, Rn <-- Rn - WR - carry ACC, Rn <-- Rn + 1 ACC, Rn <-- Rn - 1 ACC, Rn <-- Rn | (2^b) ; b = 0 ~ 3 ACC, Rn <-- reg (Rn) & (1's complement of 2^b);b =0~3 Zero/Carry Zero/Carry Zero/Carry Zero/Carry Zero/Carry Zero/Carry Zero/Carry Zero/Carry Zero/Carry Zero/Carry Zero Zero 1 1 1 1 1 1 1 1 1 1 1 1 Operation Flag Affected CYCLE
- 31 -
W562XXX DESIGN GUIDE
0 <-- 0, carry <-- Rn.3 Data Move LD Rn, i Rn <-- i, Rn : RAM mapped register (0 ~ 127) i : immediate value, 4 bit. LD Rn, k Rn <-- k, Rn: RAM mapped register (128 ~164) k : immediate value, 8 bit LDR Rn, i MV Rn, WR MV WR, Rn Branch JP label JB0 label JB1 label JB2 label JB3 label JZ label JNZ label JC label JNC label JBZ1 label JBZ2 label CJNE Rn, i,label PC <-- label PC <-- label, if ACC.0 = 1; PC <-- PC++, if not PC <-- label, if ACC.1 = 1; PC <-- PC++, if not PC <-- label, if ACC.2 = 1; PC <-- PC++, if not PC <-- label, if ACC.3 = 1; PC <-- PC++, if not PC <-- label, if PSR.0 = 1; PC <-- PC++, if not PC <-- label, if PSR.0 = 0; PC <-- PC++, if not PC <-- label, if carry flag = 1; PC <-- PC++, if not PC <-- label, if carry flag = 0; PC <-- PC++, if not PC <-- label, if Busy1 flag = 1; PC <-- PC++, if not PC <-- label, if Busy2 flag = 1; PC <-- PC++, if not ACC <-- Rn - i; PC <-- label, if ACC ! = 0; otherwise PC <-- PC++ CJE Rn, i,label ACC <-- Rn - i; PC <-- label, if ACC = 0; otherwise PC <-- PC++ CJNE Rn,WR,label ACC <-- Rn - WR; PC <-- label, if ACC ! = 0 ; otherwise PC <-- PC++ CJE Rn,WR,label DJNZ Rn,label DJZ Rn, label ACC <-- Rn - WR; PC <-- label, if ACC = 0; otherwise PC <-- PC++ ACC, Rn <-- Rn - 1; PC <-- label, if ACC ! = 0; otherwise PC <-- PC++ ACC, Rn <-- Rn - 1; PC <-- label, if ACC = 0; otherwise PC <-- PC++ - 32 Zero/Carry Zero/Carry Zero/Carry Zero/Carry 2 2 2 2 Zero/Carry 2 Zero/Carry 2 2 2 2 2 2 2 2 2 2 2 2 Rn v 3v 2v 1v 0,, vj= r * bj, r : random number (1 or 0), bj = 1 for random, j = 0~3, Rn <-- WR WR <-- Rn 1 1 1 1 1
W562XXX DESIGN GUIDE
otherwise PC <-- PC++
Mnemonics Subroutine CALL label RTN RTI Others NOP END EN INT DIS INT PLAY CH1/2, h4+voice+t4 STOP CH1/2 CLR TF0/1 No operation
Operation
Flag Affected
CYCLE
STACK <-- PC+1, then PC <-- label. PC <- STACK, used in call subroutine return PC <- STACK, used in interrupt return
-
2 1 1
BZ1/BZ2 BZ1/BZ2 -
1 1 1 1 3 1 1
Program execution stops Enable interrupt source Disable interrupt source Play voice segment used channel 1/2 Stop playing channel 1/2 TF0/1 <-- 0000B
Legend Rn: 0 ~ 63, including WR0 ~ WR7, control registers, internal registers WR: Working Register, WR0 ~ WR7 PC: Program Counter i: immediate value, 4 bit k: immediate value, 8 bit label: 0 ~ 65535 word Operator ! =: Not equal &: AND |: OR ^: XOR <--: Data transfer NOTE: ACC, Carry flag and Zero flag are modified implicitely after ALU operations.
Instruction Description
- 33 -
W562XXX DESIGN GUIDE
Arithmetic Instruction Set ADD Rn, i Description ACC, Rn Rn + i Add an immediate data i to register Rn. The result is kept in "Rn" and ACC. Flag affected: CF, ADDC Rn, i ZF1 Example ADD R10, 0011b Memory. exec. i R10 ACC Before exec. 0011b 1100b --After 0011b 1111b 1111b
ACC, Rn Rn +i + CF Add an immediate data i and CF to register Rn. The result will be kept in Rn and ACC. Flag affected: CF, ZF
ADDC R10, 0011b Memory. Before exec. exec. i 0011b CF 1 R10 1100b ACC --ADD R10, WR1 Memory. exec. WR1 R10 ACC Before exec. 1011b 1100b --After 0011b 1 0000b 0000b
ADD Rn, WR
ACC, Rn Rn +WR Add the content of WR to register Rn. The result will be kept in Rn and ACC. Flag affected: CF, ZF
After 1011b 0111b 0111b
ADDC Rn, WR
ACC, Rn Rn+WR + CF Add the content of WR and CF to register Rn. The result will be kept in Rn and ACC. Flag affected: CF, ZF ACC, Rn Rn - i Subtract an immediate data i from the register Rn. The result will be kept in Rn and ACC. Flag affected: CF, ZF
ADDC R10, WR1 Memory. exec. WR1 CF R10 ACC Before exec. 1011b 1 1100b --After 1011b 1 1000b 1000b
SUB Rn, i
SUB R11, 0101b Memory. exec. i R11 ACC Before exec. 0101b 1101b --After 0101b 1000b 1000b
1
CF denotes Carry Flag and ZF denotes Zero Flag
- 34 -
W562XXX DESIGN GUIDE
SUBC Rn, i ACC, Rn Rn - i - CF Subtract an immediate data i and CF from the register Rn. The result will be kept in Rn and ACC. Flag affected: CF, ZF ACC, Rn Rn - WR Subtract the content of WR from the register Rn. The result will be kept in Rn and ACC. Flag affected: CF, ZF SUBC Rn, WR ACC, Rn Rn - WR - CF Subtract the content of WR and CF from the register Rn. The result will be kept in Rn and ACC. Flag affected: CF, ZF ACC, Rn Rn + 1 Increment register Rn by 1. Flag affected: ZF, CF ACC, reg Rn - 1 Decrement register Rn by 1. Flag affected: ZF, CF SUBC R11, 0101b Memory. exec. i CF R11 ACC Before exec. 0101b 1 1101b --After 0101b 0 0111b 0111b
SUB Rn, WR
SUB R11, WR0 Memory. exec. WR0 R11 ACC Before exec. 0101b 1101b --After 0101b 1000b 1000b
SUBC R11, WR0 Memory. exec. WR0 CF R11 ACC INC R12 Memory. exec. R12 ACC DEC R12 Memory. exec. R12 ACC Before exec. 5 --After 4 4 Before exec. 5 --After 6 6 Before exec. 0101b 1 1101b --After 0101b 0 0111b 0111b
INC Rn
DEC Rn
SETB Rn.b
AC, Rn Rn | (2^b), b = 0~3 Set one of the register bits to 1 without altering the values of other bits. Flag affected: ZF
SETB MODE.3 Memory. exec. MODE ACC Before exec. 0000b --After 1000b 1000b
- 35 -
W562XXX DESIGN GUIDE
CLRB Rn.b ACC, Rn Rn & (1's complement of 2^b) b = 0~3 Set one of the register bits to 0 without altering the values of other bits. Flag affected: ZF CLRB IER.3 Memory. exec. IER ACC Before exec. 1100b --After 0100b 0100b
Logic Operations AND Rn, i ACC, Rn Rn & i Bitwise AND operation of register Rn and an immediate value i. The result will be kept in Rn and ACC. Flag affected: ZF ACC, Rn Rn & WR Bitwise AND operation of register Rn and WR. The result will be kept in Rn and ACC. Flag affected: ZF ACC, Rn Rn | i Bitwise OR operation of register Rn and an immediate value i. The result will be kept in Rn and ACC. Flag affected: ZF AND R2, 0010b Memory. exec. R2 i ACC Before exec. 0110b 0010b --After 0010b 0010b 0010b
AND Rn, WR
AND R2, WR3 Memory. exec. R2 WR3 ACC Before exec. 1010b 1100b --After 1000b 1100b 1000b
OR Rn, i
OR R0, 0011b Memory. exec. R2 i ACC Before exec. 1010b 0011b --After 1011b 0011b 1011b
- 36 -
W562XXX DESIGN GUIDE
OR Rn, WR ACC, Rn Rn | WR Bitwise OR operation of register Rn and WR. The result will be kept in Rn and ACC. Flag affected: ZF ACC, Rn Rn ^ i Bitwise XOR operation of register Rn and an immediate value i. The result will be kept in Rn and ACC. Flag affected: ZF ACC, Rn Rn ^ WR Bitwise XOR operation of register Rn and WR. The result will be kept in Rn and ACC. Flag affected: ZF ACC, Rn 1's complement of Rn Performs 1's complement of the register Rn. The result is kept in Rn and ACC. Flag affected: ZF OR R0, WR2 Memory. exec. R2 WR2 ACC Before exec. 1010b 0011b --After 1011b 0011b 1011b
XOR Rn, i
XOR R7, 0101b Memory. exec. R7 i ACC Before exec. 1101b 0101b --After 1000b 0101b 1000b
XOR Rn, WR
XOR R7, WR5 Memory. exec. R7 WR5 ACC Before exec. 1101b 0101b --After 1000b 0101b 1000b
NOT Rn
NOT R7 Memory. exec. R7 ACC Before exec. 0010b --After 1101b 1101b
Shift and Rotate RORC Rn ACC.b, Rn.b Rn.(b+1); ACC.3, Rn.3 CF; CF Rn.0 The content of register Rn is rotated right one bit, bit 0 is rotated into CF, and CF is rotated into bit 3 of Rn. The result is kept in Rn and ACC. Flag affected: CF RORC R16 Memory. exec. R16 CF ACC 1001b Before exec. 0010b 1 --After 1001b 0
- 37 -
W562XXX DESIGN GUIDE
ROLC Rn ACC.b, Rn.b Rn.(b -1); ACC.0, Rn.0 CF; CF Rn.3 The content of register Rn is rotated left one bit, bit 3 is rotated into CF, and CF is rotated into bit 0 of Rn. The result is kept in Rn and ACC. Flag affected: CF SHRC Rn ACC.b, Rn.b Rn.(b +1); ACC.3, Rn.3 0; CF Rn.0 The content of register Rn is shifted right one bit, bit 0 is shifted into CF, and bit 3 of Rn is replaced with "0". The result is kept in Rn and ACC. Flag affected: CF SHLC Rn ACC.b, Rn.b Rn.(b - 1); ACC.0, Rn.0 0; CF Rn.3 The content of register Rn is shifted left one bit, bit 3 is shifted into CF, and bit 0 of Rn is replaced with "0". The result is kept in Rn and ACC. Flag affected: CF SHLC R16 Memory. exec. R16 CF ACC Before exec. 1011b 0 --After 0110b 1 0110b SHRC R16 Memory. exec. R16 CF ACC Before exec. 0011b 0 --After 0001b 1 0001b ROLC R16 Memory. exec. R16 CF ACC 0101b Before exec. 0010b 1 --After 0101b 0
Data Move Instruction Set LD Rn, i Rn i Load register Rn with an immediate 4 bit value i. Flag affected: none Description LD IER, 1100 Memory. exec. i IER Before exec. 1100b --After 1100b 1100b Example
- 38 -
W562XXX DESIGN GUIDE
LD Rn, k Rn k Load internal register Rn (address 128 ~ 164) with an immediate 8 bit value k. Flag affected: none Rn v3v2v1v0,, vj= r * bj, r : random number (1 or 0), bj = 1 for random, j = 0~3. Load register Rn with a random number, which is determined by the following formula : i = b3b2b1b0 ( binary form ) Rn.j = r bj, 0j3 where Rn.j = bit j of register Rn in binary representation, r = random bit(0 or 1), which is generated by H/W, bj = bit j of "i" (4 bit, 0 - 15) in binary representation. Flag affected: none LD TIMER, 0A9h Memory. exec. k TIMER Before exec. 0A9h --After 0A9h 0A9h
* For internal register only ( address 128 ~ 164) LDR Rn, i
LDR R2, 7 Memory. exec. i R2 Before exec. 0111b --After 0111b 0rrrb
MV Rn, WR*
Rn WR Move the content of WR to Rn. Flag affected: none
MV R12, WR0 Memory. exec. WR0 R12 Before exec. 1110b --After 1110b 1110b
MV WR, Rn
WR Rn Move the content of Rn to WR. Flag affected: none
MV WR2, R10 Memory. exec. R10 WR2 Before exec. 1110b --After 1110b 1110b
Branch Instruction Set Description Example
* Data move can only be accessed between general registers (Rn) and Working Register (WR0 ~ WR7). See the Program Example for more details.
- 39 -
W562XXX DESIGN GUIDE
JP label PC label The PC is replaced with "label", and an unconditional branch occurs. Flag affected: none JP EXIT Memory. Before exec. After exec. EXIT 1A9h 1A9h PC --1A9h (In this example, the "EXIT" label is compiled to 1A9h.) JB0 EXIT Memory. exec. EXIT ACC PC Before exec. 1A9h xxx1b --After 1A9h xxx1b 1A9h
JB0 label
PC label, if ACC.0 = 1; else PC = PC++ If bit 0 of ACC is "1", The PC is replaced with "label", and a jump occurs. If bit 0 of ACC is "0", the PC is incremented. Flag affected: none
JB1 label
PC label, if ACC.1 = 1; else PC = PC++ If bit 1 of ACC is "1", The PC is replaced with "label", and a jump occurs. If bit 1 of ACC is "0", the PC is incremented. Flag affected: none
JB1 EXIT Memory. exec. EXIT ACC PC Before exec. 1A9h xx0xb 100h After 1A9h xx0xb 101h
JB2 label
PC label, if ACC.2 = 1; else PC = PC++ If bit 2 of ACC is "1", The PC is replaced with "label", and a jump occurs. If bit 2 of ACC is "0", the PC is incremented. Flag affected: none
JB2 EXIT1 Memory. exec. EXIT1 ACC PC Before exec. 1B9h x1xxb ---After 1B9h x1xxb 1B9h
JB3 label
PC label, if ACC.3 = 1; else PC = PC++ If bit 3 of ACC is "1", The PC is replaced with "label", and a jump occurs. If bit 3 of ACC is "0", the PC is incremented. Flag affected: none
JB3 EXIT2 Memory. exec. EXIT2 ACC PC Before exec. 1C9h 1xxxb ---After 1C9h 1xxxb 1C9h
- 40 -
W562XXX DESIGN GUIDE
JZ label PC label, if ACC = 0 (PSR.0 = 1); else PC = PC++ If the ACC is zero. The PC is replaced with "label", and a jump occurs. If ACC is not zero, the PC is incremented. Flag affected: none JNZ label PC label, if ACC != 0 (PSR.0 = 0); else PC = PC++ If the ACC is not zero. The PC is replaced with "label", and a jump occurs. If ACC is zero, the PC is incremented. Flag affected: none JC label PC label, if CF = 1 (PSR.1 = 1); else PC = PC++ If carry flag (CF) is "1". The PC is replaced with "label", and a jump occurs. If CF is zero, the PC is incremented. Flag affected: none JNC label PC label, if CF = 0 (PSR.1 = 0); else PC = PC++ If carry flag (CF) is zero. The PC is replaced with "label", and a jump occurs. If CF is "1", the PC is incremented. Flag affected: none JBZ1 label PC label, if BZ1 = 1 (PSR.2 = 1); else PC = PC++ If channel 1 is busy ( BZ1 flag is set to 1), the PC is replaced with "label" and a jump occurs.Else,the PC is incremented. Flag affected: none JBZ1 AGAIN Memory. exec. AGAIN PSR.2 PC Before exec. 2A0h 1 ----After 2A0h 1 2A0h JNC LOOP2 Memory. exec. LOOP2 PSR.1 PC Before exec. 300h 1 200h After 300h 1 201h JC LOOP2 Memory. exec. LOOP2 PSR.1 PC Before exec. 300h 1 ----After 300h 1 300h JNZ LOOP2 Memory. exec. LOOP2 ACC PC Before exec. 300h 0000b 120h After 300h 0000b 121h JZ LOOP1 Memory. exec. LOOP1 ACC PC Before exec. 255h 0000b ---After 255h 0000b 255h
- 41 -
W562XXX DESIGN GUIDE
JBZ2 label PC label, if BZ2 = 1 (PSR.3 = 1); else PC = PC++ If channel 2 is busy ( BZ2 flag is set to 1), the PC is replaced with "label" and a jump occurs. Else, the PC is incremented. Flag affected: none CJNE Rn, i, label ACC Rn - i; PC label, if ACC != 0; else PC = PC++ Compare the content of Rn with an immediate value i. If not equal, the PC is replaced with "label" and a jump occurs. Else, the PC is incremented. Flag affected: ZF, CF CJE Rn, i, label ACC Rn - i; PC label, if ACC = 0; else PC = PC++ Compare the content of Rn with an immediate value i. If equal, the PC is replaced with "label" and a jump occurs. Else, the PC is incremented. Flag affected: ZF, CF CJNE Rn, WR, label ACC Rn - WR; PC label, if ACC != 0; else PC = PC++ Compare the content of Rn with that of WR.If not equal, the PC is replaced with "label" and a jump occurs. Else, the PC is incremented. Flag affected: ZF, CF CJE Rn, WR, label ACC Rn - WR; PC label, if ACC = 0; else PC = PC++ Compare the content of Rn with that of WR. If equal, the PC is replaced with "label" and a jump occurs. Else, the PC is incremented. Flag affected: ZF, CF CJNE R10, 1010b, ERROR Memory. exec. i R10 ERROR ACC PC Before exec. 1010b 1011b 1A0h ----After 1010b 1011b 1A0h 0001b 1A0h JBZ2 AGAIN Memory. exec. AGAIN PSR.3 PC Before exec. 2A0h 0 1BFh After 2A0h 0 1C0h
CJE R10, 1010b, ERROR Memory. exec. i R10 ERROR ACC PC Before exec. 1010b 1011b 1A0h --0B9h After 1010b 1011b 1A0h 0001b 0BAh
CJNE R10, WR0, ERROR Memory. exec. WR0 R10 ERROR ACC PC Before exec. 1010b 1011b 1A0h ----After 1010b 1011b 1A0h 0001b 1A0h
CJE R10, WR0, ERROR Memory. exec. WR0 R10 ERROR ACC PC Before exec. 1010b 1011b 1A0h --0B9h After 1010b 1011b 1A0h 0001b 0BAh
- 42 -
W562XXX DESIGN GUIDE
DJNZ Rn, label ACC, Rn Rn - 1; PC label, if ACC != 0; else PC = PC++ Decrement Rn by 1. If ACC is not equal to zero, the PC is replaced with "label" and a jump occurs. Else, the PC is incremented. Flag affected: ZF, CF DJZ Rn, label ACC, Rn Rn - 1; PC label, if ACC = 0; else PC = PC++ Decrement Rn by 1. If ACC is zero, the PC is replaced with "label" and a jump occurs. Else, the PC is incremented. Flag affected: ZF, CF DJZ R6, start Memory. exec. start R6 ACC PC Before exec. 60h 1 ----After 60h 0 0 60h DJNZ R6, start Memory. exec. start R6 ACC PC Before exec. 60h 4 ----After 60h 3 3 60h
Subroutine CALL label STACK PC + 1, then PC label The next PC (return entry) is stored in the STACK and then the direct address "label" is loaded into PC. A subroutine is called. Flag affected: none RTN PC STACK The PC is restored from the STACK. A return from a subroutine occurs. Flag affected: none RTI PC STACK The PC is restored from the STACK. A return from an interrupt service routine (ISR) occurs. Flag affected: none Others NOP No operation. Flag affected: none NOP RTN Memory. exec. STACK PC RTN Memory. exec. STACK PC Before exec. 160h ---After ---160h Before exec. 160h ---After ---160h CALL OUTPUT Memory. Before exec. exec. OUTPUT 160h PC 40h STACK --After 160h 160h 41h
- 43 -
W562XXX DESIGN GUIDE
END The program stops execution and the W562xxx enters power-down mode. Flag affected: none EN INT This instruction enables the interrupt source. Flag affected: none DIS INT This instruction disables the interrupt source. Flag affected: none PLAY CH1/CH2, h4+vocice+t4* Use channel 1 or channel 2 to play voice segments. The voice segmemts can be the following types : 1. Speech 2. PCM Melody 3. Silence These segments can be combined arbitrarily. Flag affected: BZ1/ BZ2 STOP CH1/CH2 Stop the operation of channel 1 or channel 2 immediately. Flag affected: BZ1 / BZ2 CLR TF0 / TF1 Clear the Trigger Flag of port 0 (TF0) or that of port 1 (TF1). Flag affected: TF0 / TF1 CLR TF0 STOP CH1 1. PLAY CH2, h4+Bird+t4 ( Speech ) 2. PLAY CH1, h4+Sonatina+t4 ( PCM Melody) 3. PLAY CH1, h4+[1A0B]+t4 (Silence) DIS INT EN INT END
*
See Speech Synthesis and Error! Reference source not found. for more details.
- 44 -
W562XXX DESIGN GUIDE
Reserved Words
There are several reserved words for the W562xxx that should not be used as a normal label names. The following tables lists them. ALU ADD, ADDC, OR, XOR, AND, SUB, SUBC, DEC, INC, NOT, SETB, CLRB, RORC, ROLC, SHRC, SHLC LD, LDR, MV JP, JB0, JB1, JB2, JB3, JZ, JNZ, JC, JNC, JBZ1, JBZ2, CJNE, CJE, DJNZ, DJZ CALL, RTN, RTI NOP, END, EN INT, DIS INT, PLAY, STOP, CLR, All RAM-Mapped Registers. POI, TG, TIMER_INTERRUPT, MACRO, ENDM, DEFINE, TEST VOL 0 - VOL 7, FREQ 0 ~ FREQ 3
Data Move Branch
Subroutine Other Instructions Register Keyword Directives
SOFTWARE APPLICATIONS
This chapter provides explanations of how to use the W56000, W56xxx and instruction set features along with assembly language coding examples. Besides, some demo programs are also provided to demonstrate the functions. Users can get the object files from the example program directory and download directly to ICE system to run the programs.
Trigger Debounce
Since all P0 and P1 triggers ( total 8 pins ) share the same TG interrupt vector, users have to further differentiate the real one source from others by programming. Also, trigger debounce should be considered in the TG section. The following two assembly source code provide explanations of how to do these works by software instruction. Example 0-1 : Use only P0 as input pins. (For your reference only)
; Function :non_retriggerable W562S20 Macro INITIAL LD MODE,0000B LD IOR1,0000B LD PCR1,1111B LD IER,0100B LD PER0,1111B ENDM POI: INITIAL ; Body declaration ;macro start ; ;P1 as input port ; ;Enable TG ;Enable all P0 individual interrupt ; "POI", a keyword, Reset entry vector
- 45 -
W562XXX DESIGN GUIDE
END TG: MV WR0, P0 NOP NOP NOP NOP NOP NOP XOR P0, WR0 JNZ Bounce MV WR1,TF0 MV ACC,WR1 JB0 KEY1 JB1 KEy2 JB2 KEY3 JB3 KEY4 Bounce: CLR TF0 RTI KEY1: PLAY CH1, H4+Do+T4 JP Chkbusy KEY2: PLAY CH1, H4+RE+T4 JP Chkbusy KEY3: PLAY CH1, H4+MI+T4 JP Chkbusy KEY4: PLAY CH1, H4+FA+T4 Chkbusy: JBZ1 Chkbusy JB Bounce ;"TG", a keyword, Port 0 and Port 1 trigger interrupt entry vector
; NOP for S/W debounce time
; Check synthesizer active or not ;
- 46 -
W562XXX DESIGN GUIDE
; Function :retriggerable W562S20 Macro INITIAL LD MODE,0000B LD IOR1,0000B LD PCR1,1111B LD IER,0100B LD PER0,1111B ENDM POI: INITIAL END TG: MV WR0, P0 NOP NOP NOP NOP NOP NOP XOR P0, WR0 JNZ Bounce MV WR1,TF0 MV ACC,WR1 JB0 KEY1 JB1 KEy2 JB2 KEY3 JB3 KEY4 Bounce: CLR TF0 RTI KEY1: PLAY CH1, H4+Do+T4 JP ReleaseKey KEY2: PLAY CH1, H4+RE+T4 JP ReleaseKey KEY3: PLAY CH1, H4+MI+T4 JP ReleaseKey KEY4: PLAY CH1, H4+FA+T4 ReleaseKey: MV WR0,P0 XOR R0,1111B JNZ ReleaseKey ; Body declaration ;macro start ; ;P1 as input port ; ;Enable TG ;Enable all P0 individual interrupt ;marco end ; "POI", a keyword, Reset entry vector
;"TG", a keyword, Port 0 and Port 1 trigger interrupt entry vector
; NOP for S/W debounce time
; Check key is released or not ;
- 47 -
W562XXX DESIGN GUIDE
JB Bounce
Normally, the trigger debounce and key scan routines can be written as modules for most programs to use repeatedly. Only slight modifications are necessary to meet certain specific requirements.
Keypad Matrix Application
For applications that require a large keypad of many keys, the W562xxx family offers a direct row and column matrix of up to 8 x 9 keys. This program uses port 0 and port 1 as input ports, while port 2 and port 3 as the output ports to form the keypad matrix of 8 x 8 keys. We can also add the Vss line as another column to get a maximum of 8 x 9 keypad matrix in a direct manner. You might be able to further expand the keypad matrix by adding external resistors and diodes. This part will be collected in the application note later on.
Application Circuit
8 x 9 Keypad matrix
P0.0 P0.1
.. ............................................. .. .. ............................................. .. ............................................
W561XX
.. .. .. ..
P1.3
P2.0 P3.3 P2.1 P3.2 P2.2 P3.1 P2.3 Vss P3.0
Figure 0-1. An 8 x 9 keypad matrix diagram
- 48 -
W562XXX DESIGN GUIDE
Version A2 Date Oct. 14th, 1999 Writer Sophia Ho Reasons for change * Add two body with two chips solution W562M-04 W56000+W55M08 W562M-05 W56000+W55M06 * modify TXF register table on page15 * remove the software application about volume control
A3
Nov. 18th, 1999
Sophia Ho
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792697 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
- 49 -

▲Up To Search▲

Price & Availability of W562XXXDESIGNGUIDE

	To Download W562XXXDESIGNGUIDE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .